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I've made that point before on YC.[1] We need to view fast storage as something other than a disk accessed through the OS, and other than slow RAM accessed as raw memory. Access through the OS is too slow, and access as raw memory is too risky. What's probably needed is something like a GPU sitting between the CPU and the fast persistent storage. Call this an SPU, or "storage processing unit."
What would such a device do? Manage indices, do data transformations, and protect data. Database-type indices would be maintained by the SPU, so applications couldn't mess up the database structure. The SPU would manage locking, so that many non-conflicting requests could be serviced simultaneously. The SPU would have tools for doing searches. Regular expression hardware (this exists) would be useful. Record protection management (app can read/write part but not all of a record) would allow implementation of database type data access rules. Encryption and compression might be provided in the SPU.
There have been smart disk controllers before, but they haven't been that useful, since they couldn't make the disk go any faster. Now, it's time to look at that layer again. Some of the technology can be borrowed from GPUs, but existing GPU architecture isn't quite right for the job. An SPU will be doing many unrelated tasks simultaneously. GPUs usually aren't used that way.
Being up front: this is what I work on for IBM Systems. A buddy wrote this blog (https://www.ibm.com/developerworks/community/blogs/fe313521-...) with a little more info.
What we have is an IO offload accelerator that knows how to drive high bandwidth IOs to some external storage device. A user app doesn't interact with the device - they make shared library calls to read or write data from a particular buffer, and the accelerator (because it's cache coherent) can read / write from the virtual address space of the user space program to satisfy the request as needed. This means that the IOs bypass the entire OS driver stack, since everything is a shared library call from user space.
So yep! That exists. :-) There's other classes of accelerators out there too (and coming in the future as well). Adding additional function like compression or some form of indexing or search is stuff that we've talked about.
(edit) - https://github.com/open-power/capiflash has the code for the shared libs, the APIs, and some examples.
(Disclosure: one of the authors here)
Wrapping a bunch of replies into one: Absolutely agree that we need to view fast storage as something other than disk behind a block interface and slow memory, especially with all the different flavours of fast persistent storage that seem to be on the horizon. For the one's that attach to the memory bus, the PMFS-style [1] approach of treating them like a file-system for discoverability and then mmaping to allow them to be accessed as memory is pretty attractive.
I'm not sure a dedicated storage processing unit is the way to go though; I think we could equally well see bits of functionality being offloaded to smarter controllers (kind of like checksum, VLANs, etc are on network adapters) while the CPU remains in charge of orchestrating the different bits.
Also agree on the fact that it is an interesting data structure problem -- a lot of the work we do involves examining what the right data structures are for things once seeks are free and cache locality is the dominant factor for operations.
This sounds interesting, but why should this be a new piece of hardware as opposed to a new OS service? Are these functions simply so specialized that implementing them in the OS would be a bottleneck (even though the CPU has plenty of free cycles)?
Just to clarify: this is to enable programs to have more a more direct and faster interface to data, while retaining data consistency and safety that typically would be managed by the OS?!
Is this not just another form of DMA (direct memory access)? And if so, how would it differ from current implementations? Sometimes DMA only refers to ram, though on many systems this is fluid between different data storage types (AMDs direct compute comes to mind), exactly to enable this kind of data access.
This looks like the perfect job for an FPGA (with a fast enough interconnect, poster above mentions CAPI which sits on top of PCIe but I have not had a chance to try it out yet).
Sound similar to Channel I/O.
If you're going to have database-like features, might as well just make the entire machine a dedicated database server.
Having a database engine accessing the entire storage device (in a shared-memory like setup) is no more dangerous than having a database engine accessing all of its own memory and disk.
So we can have one server for SQL-like things, one more server for NoSQL like things, and one more server for storing blobs. And that's that.
isn't this basically what Channel IO is?
This is so true, the world has changed greatly and not everyone has gotten the memo. I saw a really cool device made by Texas Memory systems which was a "ram disk" that was all ram with disk backing, and when you lost power it flushed to disk. I wanted something that worked better for a storage paradigm and designed/invented a network accessible memory appliance[1]. Basically using ethernet packets you could store 8K integrity protected chunks right there on the network. Initially I wanted to use a typical low power CPU with a bunch of DRAM attached but the CPU bottleneck got in the way, so we redesigned/rebuilt it out of FPGAs so that it had a couple of terabytes of RAID protected RAM in an appliance with a very simple network protocol for storing and fetching 8K blocks out of what was essentially a linear address space. Two of these on different power subsystems provided all of the fault tolerance you needed and you could have a terabyte of 'structured' data live from the moment your computer booted (made for very fast recovery from reboot).
That is fascinating. Could this reliably reduce the hardware footprint on any device?
My sense is this is only true today because OS kernels are ridiculously slow relative to what the hardware can achieve.
Most of my recent designs treat RAM as if it were (what we used to considered to be) disks, i.e. all computation and in-process data is in cache exclusively, and "going to RAM" requires the use of a B-tree-like structure to amortize the cost.
For example, once you've opened a RAM page line on a normal four-channel Xeon server, you can read the entire 4KB page in about the same time it takes to read one byte, switch pages, and then read another byte. (Of course, you can't do that either since the entire cache line will be filled, but the overall point still stands.)
The situation we're in today with RAM is pretty much the identical situation with the disks of yore. Anyway…interesting article nonetheless.
Right, modern CPUs can do 50 gigaflops per core. There's absolutely no chance we're going to have non-volatile storage that can do hundreds of billions of IOPS any time soon (if only because you won't be able to get that much data over PCI-express).
Further given you can saturate 16 lanes of PCIe when talking to a GPU there's no reason you shouldn't be able to do the same for storage, it's just a matter of having the right abstractions and the right kind of thinking like you're saying.
It sounds more like storage and RAM are going to converge (and people are still learning to deal with how slow RAM is compared to the CPU these days).
Not that is some interesting thinking. You got a blog post elaborating on this?
Yeah per packet processing at 40Gbps and higher is problematic on regular kernels, OS stack and CPUs. A lot of really can be cache hits -- hundreds of nanoseconds. Article mentions that too:
--- To put these numbers in context, acquiring a single uncontested lock on today's systems takes approximately 20ns, while a non-blocking cache invalidation can cost up to 100ns, only 25x less than an I/O operation. ---
It also depends if workload is throughput sensitive or latency sensitive. If it is latency, can do things like tie processes and interrupts to cores, isolate those cores, etc. For throughput can processes more than one packet at a time perhaps.
Then there is dpdk and even unikernels.
> CPU has responsibilities beyond simply servicing a device—at the very least, it must process a request and act as either a source or a sink for the data linked to it. In the case of data parallel frameworks such as Hadoop and Spark,7,17 the CPU
That's why you get more CPUs and explicitly isolate them if you can. But now depending on how they share data with other CPUs there will be invalidated cache lines so will pay that way as well.
In general if you run on RHEL / CentOS ( a lot banks, military and enterprise deployments do ), there is this helpful guide as an overview:
https://access.redhat.com/documentation/en-US/Red_Hat_Enterp...
Cache miss latency was the first thing that popped into my mind as well when I saw the title.
It seems like they don't make a clear distinction between latency and bandwidth. From the little I know on SSDs(don't claim to be an expert here) the sequential reads are below or on-par with high spindle speed disks.
What seems to be a better take-away would be that sequencing of your reads isn't nearly as important as it used to be. Back in games we'd duplicate data across a DVD so that we could do "seekfree" loading where duplicating 5-10MB of data would mean just a single big call to read() and gain massive load time performance.
I have just bought a machine with one of these drives and a bunch of GPU's with the intent of running tensor-flow on it. Do you think that Fedora will allow for the kind of tuning you describe or should I stick with Centos? I was thinking that I would need Fedora because these new devices need new kernels and drivers and so on, but maybe I am just confused?
I like the article, but not your title. It implies that this trend of I/O becoming highly performant has occurred recently, when in fact has been observed and studied for quite some time [0, 1]. Even before SSDs Gigabit ethernet was saturating CPUs needing to do more than DMA a packet, and I'm sure this trend continued for some time. The original title seems more accurate: "Implications of the Datacenter's Shifting Center", and references the existing trends in an insightful article.
[0] http://ucsdnews.ucsd.edu/archive/newsrel/supercomputer/11-09...
So NVDIMM's...
Is any one actually making those except Viking and is anyone actually supporting them in servers except SuperMicro?
These are basically DDR3/DDR4 DIMM's with onboard flash and a supercap/battery pack to provide persistence incase of system reboots and power failures.
They are also a bit odd as they would ignore various system event calls from the BIOS/UEFI and then have to be specifically managed by various software hacks that create RAM drives and access the memory directly rather than working with OS virtual memory. Since NVDIMM's are basically treated as system memory by both the server and the OS they pretty much only work for very very boutique applications I'ts a bit odd that these are presented as the next step in storage evolution while being effectively an overpriced hack. I've only seen them actually been use in weird server setups like the overclocked watercooled servers that are used for HFT where they strip everything even the OS as possible and bypass anything that adds even a few NS of latency and don't mind running their own code for everything from a bastardized TCP stack that isn't even remotely compliant but works to their own in memory custom database.
Intel will be pushing them hard starting with Skylake-EP, so some people are getting themselves ready.
This trend has been clear for awhile. Interestingly, this will put performance pressure back on programming and languages as they become the "new" bottleneck.
I'd expect an implicit migration away from slower languages toward faster ones.
To some extent, yes, but 'slow' languages usually delegate batch work over large datasets to optimized libraries.
Even more likely, as I see it, is this contributing to the increasing rise of tools like spark, hadoop, etc. Slow languages will continue to be popular as orchestration around these tools.
Both Tandem DP2 and IBM Coupling Facility on zSeries Sysplexes worked exactly like how you envisage an SPU would work. Therefore, when we developed RDMA-attached persistent memory at Tandem in 2002, we put it under the control of DP2/ADP process pairs. Later, we ported it to HP-UX and InfiniBand RDMA. There is one paper at IPDPS'04 and several published patents you can look up in my Google Scholar page. pmem.io crowd is reinventing some of this wheel. If any of you work at HPE, you can find much more detailed internal papers, source code, drivers, firmware, and other stuff that the outside world cannot get to.
> and the performance of an SCM (hundreds of thousands of I/O operations per second) is such that one or more entire many-core CPUs are required to saturate it.
So, we are getting a lot of data, but latency is still killing. (Even more taking into account that this thing has a few stages of pipeline inside.)
Anyway, our CPU is getting distributed nearer IO and memory. We are going to get NUMA machines, everything points at it.
Knights Landing from Intel is already NUMA (I think). I'm not sure if it can be bought yet, but it should be very close to release.
Please excuse my ignorance on this matter but will this technology have any impact on the hierarchy levels below disk (i.e. RAM and CPU caches)? Compared to Register, L1 and L2 access RAM access is still really slow. Will non-volatile storage latencies rival or exceed those of standard RAM? From how I understand the article it's primarily disk IO speed that's affected, correct?
Yes. Even the persistent memories that attach to the memory bus are currently quite a bit slower than DRAM (5-7x from estimates I've seen), while the difference with PCIe-attached ones is even more.
I'm not sure what the future holds in terms of latencies for non-volatile storage but sub-DRAM levels aren't within reach yet.
For anyone else who was momentarily confused: on figure 2, the y-axis scale is incorrectly labeled "ns" when it should be "ms".
Anyone old enough will remember the time hard drivers were correctly marketed with access time in milliseconds as the main speed indicator. This ended around 1994() when pretty much all the drives reached ~10ms access time.
https://en.wikipedia.org/wiki/Hard_disk_drive_performance_ch...
I did a quick scan of old computer magazines (infoworld, pc mag etc).
HP was designed a "flat memory" OS based on vast amounts of cheap memrister memory http://www.technologyreview.com/featuredstory/536786/machine....
But when I googled gfor this article I saw the project has been delayed.
I'm very interested in working on a "flat memory" OS that doesn't use any RAM or file system but simply registers and a distributed database of key/value stores.
If you're interested in talking about this more (especially if you're in the SF Bay Area), my email is in my profile.
I'm seeing this on a new Postgres database server: my cache miss and cache hit queries take virtually the same time!
This is with a Skylake Xeon E3-1275, 64GB ECC UDIMM, and Intel 750 PCIe SSD (probably the fastest setup you can get).
It looks like I have to figure out something that tunes Postgres to account for the fact that disk lookups are no-cost.
> I'm seeing this on a new Postgres database server: my cache miss and cache hit queries take virtually the same time!
That's likely because it's hitting the OS's page cache.
Serious but naive question: does a bottleneck curve trending toward CPU subsystems suggest micro kernel based approaches replacing spinning up virtual machines as a future trend due to the possibility of reduced overhead at the CPU?
tldr; Does increasing use of Storage Class Memory imply increasing use of microkernals?
The numbers in this are daunting, but I personally believe massively multi-core systems make the problem a lot less daunting than the article makes out. Core counts in big servers can get up over 100 per server for Intel (see Amazon's new EC2 offerings for public evidence of this). Intel's Xeon Phi series of processors offer core counts approaching ~300. Going to 300x takes the required latencies per request from microseconds up to the millisecond range. POWER systems can go even higher. Moreover, for many workloads that actually leverage this sort of compute you can do something horrifying with the new DRAM-addressable persistent storage: DMA directly from the NIC into block storage. Some (many?) high performance network adapters offer the ability to filter packets to distinct Rx queues; buffers can be posted with addresses in the storage mapped region allowing direct NIC->storage transfer. If you bake more intelligence into the NIC, you can even do things like Mellanox's NVMe Fabrics:
http://www.mellanox.com/blog/2015/04/mangstor-mellanox-show-...
This is particularly relevant to the JBOD example.
Now, there's the question of what you're actually going to do with all of that data, but in a lot of cases it's likely a durable read-mostly cache that's effectively a materialized view optimized of some (hopefully much slower write-rate) transactional store (say, product data on Amazon -- detail pages served up at some absurdly high rate, but a relatively low mutation rate).
Other workloads I can think of fall into a category I tend to think of as log processing -- a high-rate series of streaming writes which are slurped up and batch processed/reconciled to some (much smaller) state (which of course may then be exploded back out to large materialized views as above). In these scenarios, presuming the log entries have low contention over the underlying state, CPUs like those I called out above are more than up to the task of streaming over the input and optimistically updating the backing state.
Finally, in terms of real workloads, there is almost always going to be a bottleneck limiting your ability to fully utilize your resources. Either you're CPU bound and leaving network bandwidth on the table or you're network bound and are leaving CPUs/storage devices under-utilized. Massively improved storage performance local to a node is fantastic in terms of computation you can do locally, but if each network fabric upgrade costs you 10x what the previous one did to keep up with the storage/CPU available per-node, you're going to have a bad time. Amin Vahdat talked a bit about our (Google's) historical network fabric evolution: https://www.youtube.com/watch?v=FaAZAII2x0w
If I were betting on an annoying bottleneck to full resource utilization coming up in the near future, I'd put my money on network before CPU :)
Increasing industry trend to expose CPU / GPU / SPU / NPU directly to applications for more efficient data handling.
Performant: still not a word.
Seymour Cray never said "performant". Engineers say "fast" or "fast enough". Marketing types and nontechnical management seem to prefer this neologism. But it might also be a generational thing.
A new coinage that I noticed in the past year that also grates on my ears: "learning" as a substitute for "lesson", as in "what were your learnings from the hackathon?" Anyone else caught this one?
This is the worst use of the neologism I've yet seen:
(1) It's not perfectly clear what the definition is in this particular context. Usually the word is used to indicate "our stuff is rad fast bro" implying that speed is obtained through cleverness such as the use of efficient code or an efficiently scalable architecture, but the linked article violates this definition by comparing apples (CPUs) and oranges (storage). It's nonsensical in the manner of "my word processor is more performant than my fractal renderer".
(2) Normally, use of this neologism saves time by replacing a long phrase. This use in the linked article is backwards: the word "faster" could have been used in place of the longer "more performant."
How do you think new words came about?
A by-product of "high-performance" being coopted a long time ago by "high-performance computing." Seems to me to be a natural part of the evolution of technology.
Not sure it'd explain the origin of the use of this word in english, but performant is a french word that is very often used in this context.
This word is one of my pet peeves as well. "Performant" is an ignorant and foolish way to say "high performance". It's like saying "voltant" instead of "high voltage". I'm all for coining new words that mean new things, but when someone says "performant" I treat it as a clue that they might be a sloppy thinker.
Thank you.