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This a great example of horizontal microcode.

Vertical microcode like you see in modern microcoded cores looks a little different and was really well documented by these guys: https://media.ccc.de/v/34c3-9058-everything_you_want_to_know...

Unfortunately I couldn't get mythsim to load. Does anyone know of any mirrors for this?
Yep. I used to design and build exactly that in the 70s and 80s. Some people thought we were crazy or gods but I had the mindset and loved it.

Today's gluing together of modules and blocks is boring in comparison.

>"Today's gluing together of modules and blocks is boring in comparison."

Can you elaborate on this? Aren't microcoded CPUs still around?

Author is probably alluding to a shift to SoC-driven design where they mix and match silicon components like programmers do third-party libraries. They stitch black-boxes together much of the time. With all the synthesis, they also spend more time driving black boxes that generate the circuits rather than hand-making parts of them.

As a non-hardware guy, I'm still wondering why microcode isn't more popular. It's flexibility is great. Especially if the company has a HLL-to-microcode compiler so the users can create custom instructions. I know they like to change microarchitecture around. They could say they refuse to support anything below the ISA with backward compatibility. Customers will have to port their microcode extensions to each new hardware. That said, you can do some neat stuff with it like people did with PALcode on Alpha. You can bend the ISA to your application or even make certain instruction combos atomic. I remember using microcode for crypto gave performance boosts, too.

Custom instructions is what Tensilica Xtensa "configurable cores" about. That's different from the custom instructions you are talking about in that the technology is all about pre-fab stage, that is possible to add custom instructions on levels lower than microcode, but still it's hardcoded into the "customized" CPU. The main problem with the technology is still C compiler support for added custom instructions.
On something like Skylake, your complicated instructions would execute out of MS-ROM and they would confuse the hell out of the hardware scheduler. Alternatively, you could write simple instructions which would get translated into μops and cached into μop store.

FPGAs are a better and saner approach to user programmed performance acceleration. User microprogramming has never worked. It's a maintenance+security nightmare for everyone.

What is MS-ROM? I am not familiar with this, is it specific to SKylake?
That's Intel's term from the Intel® 64 and IA-32 Architectures Optimization Reference Manual. MS-ROM stands for microcode sequencer ROM. Complicated instructions aren't decoded from x86 into μops. They're read from the MS-ROM (what Fog calls the microcode ROM). They pollute the μop cache. Basically, they support the really complex instructions but that's it.

Clearly the ROM is a ROM and read-only and I mistakenly said that user microprograms would be written there. No, they'd be written to a WCS, Writeable Control Store.

All that said, the Intels + ARMs of the world would hate this idea. You'd be eeking out a wittle bit of performance at significant support cost. They'd just tell you to buy a faster or another CPU.

User programmable WCS was an idea from the 80s. But now, it's a bad idea. If it were a good idea then Microsoft or Google or Amazon would be all over it because they have the capital, the leverage and the need to do it. Yet they don't.

Thanks yeah that makes sense.

>"As a non-hardware guy, I'm still wondering why microcode isn't more popular."

I have the same thought. There must be a reason for this. Maybe someone else could provide some insight.

>"That said, you can do some neat stuff with it like people did with PALcode on Alpha"

I'm not at all familiar with this. Might you have some links or resources regarding this? Cheers.