The other day, I watched this talk, which at that time had 473 views (and now has just over 500): https://www.youtube.com/watch?v=gAIOy7MucYI
In it, Dan Lickly says people are more interested in his time on a submarine than his work on Apollo. I thought this was disheartening.
A spacefaring billionaire and a genius engineer who sent men to the moon talk for an hour, and it only gets 500 views. What a world.
Here you guys are helping the AGC pass it's self-tests, which was an amazing step.
https://www.youtube.com/watch?v=HpIwQZaEvV0
I worked on a core memory device when I was in the Air Force, and got to troubleshoot a problem with it (which was rare - it was usually very reliable). One core had gone bad in a particularly poor location, which corrupted the "end of message" indicator. So we'd get one message and it would hang, waiting forever for the message to end!
https://nara.getarchive.net/media/ssgt-anthony-j-mathis-and-...
(neither of them are me)
An automated process is only better than humans because it is repeatable. However it can still repeatably do the wrong thing!
Do you have any insight into what was the design process for such a safety critical device and how provable was it's 'correctness'?
If you lost power after a read and before the rewrite would your ROM get corrupted?
It seems like the actual information should be in the weave pattern. Or, was there a reset line that reset all the cores at once?
The physical difference between ROM and RAM core memory is not entirely clear to me. If I read it correctly, what causes something to read as 1 or 0 depends on whether the wire was wired through or around the core. How does this work for RAM then?
RAM is addressed in an X-Y grid, using core's "coincident current" property. An X line gets half the current necessary to flip a core, and a Y line gets half the current, so only the core where both cross gets flipped. When writing a core, the core is flipped to the 1 state unless an inhibit line blocks it, causing it to stay in the 0 state. Core rope, on the other hand, uses inhibit lines for addressing, blocking all cores except the desired one.
Another key difference is RAM stores one bit per core, while rope (ROM) stores 192 bits per core, making it much more dense. (Each rope core has 192 sense wires passing either through or around it.)
RAM uses tiny ferrite cores, while rope uses much larger cores consisting of a permalloy ribbon wound around a bobbin.
RAM uses a separate plane of cores for each bit in the word, while all the bits of a word share the same core in a rope.
Both RAM and rope use sense wires threaded through the cores, along with sense amplifiers to pick up the weak signals.
I've written about the AGC's RAM core memory here: http://www.righto.com/2019/01/inside-apollo-guidance-compute...