But there are still a lot of useful parts in SV. I thought of creating a kind of "Verilog 20" which just incorporates the useful synthesizable features from SV including parts of SVA and interfaces. I would even consider to leave out parts of Verilog which are not synthesizable and use a different language for verification altogether (e.g. C++ or Python as e.g. with Cocotb).
I recently came accross Wirth's Lola and even built an IDE for it (https://github.com/rochus-keller/LolaCreator), but its practicality and usefulness is still to be demonstrated and the compiler has issues.