Xeon Phi was always a very targeted and limited product for HPC. Nobody was doing tons of performance-sensitive JSON parsing or emulating a PS3 or ARM on a Xeon Phi. Emulator people aren't going to target hardware that doesn't exist in their target market.

In practice the first time AVX-512 was accessible to the general public was Skylake-X, so 2017. Five years ago. And it was a server/HEDT product. And it had some weird performance regressions (like the downclocking or pausing when you use too many heavy instructions) that bumped it back out of a lot of codebases it might have hypothetically been useful.

The first consumer architecture that would have implemented it was massively late due to 10nm delays. So was the 10nm successor to Skylake-X that fixes the downclocking and other shortcomings.

Basically the answer here is "10nm". AVX-512 is a casualty of the eternal 10nm delays. Intel got stuck on Skylake forever, and couldn't push any of their other developments forward. They've had fixes for a while for a ton of the stuff people complain about, they just couldn't manufacture them at scale.

They are only just launching their first post-14nm server platform literally this year, and it's not even Intel 7/10nm ESF, it's Ice Lake based lol.

Initially AVX-512 was known as "Larrabee New Instructions".

This instruction set, which included essential features, which have been missing in both earlier and later Intel ISAs, e.g. mask registers and scatter-gather instructions, was developed a few years before 2009, by a team in which many people had been brought from outside Intel.

The "Larrabee New Instructions" have been disclosed publicly in 2009, then the first hardware implementation available outside Intel, "Knights Ferry" was released in May 2010. Due to poor performance against GPUs, it was available only in development systems.

A year later, in 2011, Sandy Bridge was launched, the first Intel product with AVX. Even if AVX had significant improvements over SSE, it was seriously crippled in comparison with the older AVX-512 a.k.a. "Larrabee New Instructions".

It would have been much better for the Intel customers if Sandy Bridge would have implemented a 256-bit version of AVX-512 instead of implementing AVX. However Intel has always attempted to implement as few improvements as possible in each CPU generation, in order to minimize their production costs and maximize their profits. This worked very well for them as long as they did not have serious competition.

The next implementation of AVX-512 (using the name "Intel Many Integrated Cores Instructions"), was in Knights Corner, the first Xeon Phi, launched in Q4 2012. This version made some changes in the encoding of the instructions and it also removed some instructions intended for GPU applications.

The next implementation of AVX-512, which changed again the encoding of the instructions to the one used today, and which changed its name to AVX-512, was in Knights Landing, which was launched in Q2 2016.

With the launch of Skylake Server, in Q3 2017, AVX-512 appeared for the first time in mainstream Intel CPUs, but after removing some sets of instructions previously available on Xeon Phi.

AVX-512 is a much more pleasant ISA than AVX, e.g. by using the mask registers it is much easier to program loops when the length and alignment of data is arbitrary. Unfortunately the support for it is unpredictable, so it is usually not worthwhile to optimize for it.

Hopefully the rumors that Zen 4 supports AVX-512 are true, so its launch might be the real start of widespread use of AVX-512.