Item — HN Reader

We know this for a long time. Few years down the road in sub 10nm, we will reach the era where we cant shrink transistor endlessly. The problem with chip stacking on die is how to get rid of the heat passing through each layer.

Stacking in itself has proven to be feasible by the Memory Cube. Where Heat isn't much of a concern.

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I expect that what we'll see is a top layers of general purpose processing on top next to the heat sinks, then lower power layers further down, like maybe a layer of L3 cache then a stack of main memory. Probably also a lot of dark silicon which is only lit up for special tasks, like media encoding or encryption.