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It’s fun to be just a curious bystander for many years in this industry.

Every now and then Moore’s law hits a roadblock. Some experts see that as a clear sign that it’s reaching its end. Others that it’s already dead, because actually, the price per transistor has increased. Others that it’s physics, we can approach Y but after X nm it can’t be done.

Then you read others that claim that Intel has just been lazy enjoying its almost monopoly for the past decade and was caught off guard by TSMC’s ultraviolet prowess. Or people who really know how the sausage is made, like Jim Keller, enthusiastically stating that we are nowhere near any major fundamental limitation and can expect 1000X improvement in the years to come at least.

Anyway, it’s really fun to watch, like I said. Hard to think of a field with such rollercoaster-like forecasting while still delivering unparalleled growth in such a steady state for decades.

The limitations are very real. Dennard scaling has been dead since the mid-2000s (that is, power use per unit area has been increasing, even though energy use per logic operation is very much dropping at leading edge nodes) which means an increasing fraction of all silicon has to be "dark", power-gated and only used for the rare accelerated workload. Additionally, recent nodes have seen very little improvement in SRAM cell size which is used for register files and caches. So perhaps we'll be seeing relatively smaller caches per core in the future, and the addition of eDRAM (either on-die or on a separate chiplet) as a new, slower L4 level to partially cope with that.
>It’s fun to be just a curious bystander for many years in this industry. Every now and then Moore’s law hits a roadblock. Some experts see that as a clear sign that it’s reaching its end......

That is just mainstream reporting.

If one actually went and read the paper referred or what the context was. It was always the same thing. It was all about the economics, all the way back from early 90s. We cant do x node because it would be too expensive to sustain it at a node every two years.

Smartphone era ( Referring to Post iPhone launch ) essentially meant we ship an additional ~2 Billions Pocket computer every year including Tablet. That is 5x the most optimistic projection to traditional PC model at 400M / year. ( Which we never reached ). And that is ignoring the Server market, Network Market, GPU market, AI Market etc. In terms of transistor and revenue or profits the whole TAM ( Total Addressable Market ) went up at least 10x more than those projection. Which is essentially what scale us from 22nm to now 3nm, and all the way to 2nm and 1.4nm. And my projection of 1nm by 2030 as well. I even wrote on HN in ~2015 I have a hard time to see how we could sustain this post 3nm. At the time when trillion dollar company was thought to be impossible.

On the other side of things, the cost projection to next node ( e.g 2nm ), and next next node (e.g 1.4nm ) was always higher than what its turns out. As with any large project management it is was better to ask and project more in case shit hits the fan. ( Intel 10nm ) But every time TSMC has executed so well.

So as you can see there is a projection mismatch at both ends. Which is why the clear sign of progress coming to end keeps being wrong.

> and can expect 1000X improvement in the years to come at least.

I just want to state that this figure keeps being throw around. It was Jim Keller comparing at the time Intel 14nm ( Which is somewhere close to TSMC N10 ) to hypothetical physics limit. At 3nm we are at least 4x pass that. Depending on how you want to measure it we could reach less than 100x by 2030.

AI trend could carries us forward to may be 2035. But we dont have another product category like iPhone. Server at hyperscaler are already at a scale growth is slowing. We will again need to substantially lower the development cost of leading node ( My bet is on the AI / Software side ) and some product that continues to grow the TAM. May be Autonomous Vehicles will finally be a thing by 2030s ? ( I doubt it but just throwing in some ides ).

Aren't Intel, TSMC and Samsung all customers (and investors) of ASML, which is actually the manufacturer and developer of the EUV (ultraviolet) machines this refers to? Basically, if at all, they might have a slight exclusivity deal, but given the owner structure you can imagine that this will not really affect anything in the long run. With the willingness of spending the money on new nodes they will have the technology too.
As Jim Keller himself famously put, Moore's law is still fine. Furthermore, the number of people predicting end of Moore's law doubles every 18 months, thus following the Moore's law itself.
It is fun to watch and keep track of - And keeping in mind it's also been an insane amount of work by an insane number of people with an insane amount of budget thrown at the problems. You can do quite a bit in software "as a hobby" - and this field is not it.
Fun times.

I think one of the interesting takeaways here should be that they have a 48 - 50nm "device pitch" which is to say the transistors are small in the XY plane there are pitch widths much larger than "5nm" or "3nm" (people familiar with chip production realize this but too often people who don't have a very deep understanding of chip production are mislead into thinking you can put down transistors 5nm apart from each other)

So from a density perspective, a perhaps 30 - 40% gain in overall number of transistors in the same space.

Looking at the Intel inverter design, it looks like if they were willing to double the depth they could come up with a really compact DRAM cell. A chiplet with 8 GB of ECC DDR memory on it would be a useful thing both for their processors and their high end FPGA architectures.

really compact DRAM? have you seen DRAM? the aspect ratio is already huge, though afaik no one stacks the pass transistor.

high-end systems already have stacked DRAM chiplets, though admittedly this hasn't made much of an appearance outside GPUs until now (MI300a).

General question about semiconductors: Why is there so much emphasis on the density of transistors rather than purely on the costs of production (compute/$)? CPUs aren't particularly large. My computer's CPU may be just a few tablespoons in volume. Hence, is compute less useful if it's spread out (e.g., due to communication speeds)?
Light travels at one foot per nanosecond. So a processor one foot wide you'd expect to run at 1 GHz max.
You could always purchase a multi CPU system (effectively what you're suggesting) from several years ago for much cheaper than modern hardware. If you're using it regularly though, the electrical cost will eventually eat away any money savings vs the same computational power in a modern single CPU.
It is?

A factory makes transistors ,and if you increase a 'node', you make twice as much. If you do an amazing job, you might reduce cost 10%.

So by far the best way to maximize value in semiconductors is to enable shrink.

But you also just don't hear it in the popular or even engineering press. Most manufacturers and designers look at a PPAC curve (power, performance, area, cost) and find optimal design points.

As for spreading it out: the unit of production isn't a wafer, it is a lithographic field, which is roughly 25*35mm. You cant practically 'speead out' much more (ok, you sort of can with field stitching, but that is really expensive).

Because when you make it denser, you can cut the CPU into smaller parts, which decreases costs

when you make it less dense, it can clock up higher, but you will have fewer cores per mm^2

AMD went with both approaches, where their hybrid CPU will have densely packed low speed Zen 4C cores and some high speed Zen 4 cores to boost at the highest frequency

In addition to the answers already given, there are defects during the process that are more likely to render your chip useless the larger your chip is. This is true for smaller chips as well, and often the design handles a defunct component, but you prefer minimizing defects per chip.
Density is one of the main ways to get cost savings. But there are others too, and there's also a lot of hype around them. Chiplets for example. Or CXL for memory.
Personal usage still relies on fast single threaded performance. As far as business usage, the cost is primarily energy which requires smaller node size for the same performance.
Because you are assuming there is an objectively optimal processor design for a specific manufacturing process.

If you don't constrain the chip to a specific design then what is going to count as compute? The number of adders or multipliers? That is just a different way of talking about transistor density.

What do you mean by spread? Multi socketed mainboards?

That would help only for parallelizable workloads. For many workloads is the single threaded performance that matters most.

cost is area, because defects.

TOF latency isn't that much of a big deal, though driving a signal for distance consumes a lot of power, and power has been the primary design-limiter for at least a decade.

Yes, electricity doesn’t move instantly
reducing costs is nice for consumer… making cpu higher cost that goes brrrrt is better for business
I believe this was some of the advantage of the AMD Zen series of chips which moved to a larger die size from Athlon.
the physical limitation of more CPUs: heat, which in turn downgrades performance
Maybe I’m missing something here, but wouldn’t heat become a bigger issue? Right now we have pretty intense cooling solutions to get heat off the surface of a comparatively thinner chip. If chips become more cubic how would we cool the inside?
If we keep going down this route I have to wonder if we'll see something drastic in the cooling space.

CPU dies are optimised towards being cooled from one side. I wonder if we'll eventually see sockets, motherboards and heat spreaders shift towards cooling both sides of the CPU.

Probably not, can't imagine what a halfway feasible solution to integrating pin out and a heat spreader would be.

In storage, moving away from 2D MLC and TLC NAND towards 3D TLC stacking (and horrendous higher bits) has introduced disturbances that literally shorten the memory life cycle. When a cell is read, the voltage alters the state of adjacent cells, which must be forced to be rewritten to preserve their state, thus shortening the life cycle of the disk just by reading data. they are selling us crap.

From the little I understand about the problem, this would be solved by occupying more surface area to separate the tracks that run through the vertical stacks ? what would be like a 2D design surface area but with bigger complications. Although I have read papers[1] that propose adding latency in an attempt to mitigate (not solve) the problem.

So now, reading this news about processors and stacking, I wonder about what inconveniences the end users are going to suffer with processors built under these techniques. Whether in computational reliability, vulnerabilities and so on.

I wrote vulnerabilities (pure imagination and speculation of my own, I'm imagining a prefetch problem at the transistor level) because if it turns to be real at future I can see the manufacturer introducing a fix for randomly increase latencies or any other thing, and sending the computing power back ten years with an "oh, we didn't expect it such thing were possible when we designed it".

And of course the computational reliability.

is being taken care of to avoid all of this?.. if not, I leave my comment here for courts in the future.

[1] [2021] doi.org/10.1145/3445814.3446733 (use sci-hub)

[2] [2018] doi.org/10.1145/3224432 https://people.inf.ethz.ch/omutlu/pub/3D-NAND-flash-lifetime...

>So now, reading this news about processors and stacking, I wonder about what inconveniences the end users are going to suffer with processors built under these techniques. Whether in computational reliability, vulnerabilities and so on.

Denser logic hasn't got the same issues as dense non-volatile storage as logic doesn't need to have any persistence.

It's what the likes of Micron and Samsung are good at fixing and working around when they launch and scale their Xnm processes for a specific storage technology, and what makes them better than competitors.

Intel, TSMC, GloFo, etc they all can buy the latest gen EUV machines from ASML if they want, but yet TSMC is always one node ahead on logic and Micron and Samsung win at storage, because they're good at ironing out the kinks and challenges that come from shrinking down those specific designs closer and closer to sub-nm level while the others can not (so easily).

If fabbing cutting edge silicone was as easy as just having the latest gen ASML machines, then ASML would just hoard the cutting edge machines for themselves and become vertically integrated in fabbing their own cutting chips as a side hustle before everyone else.

> they are selling us crap.

You can completely rewrite a modern 4TB 3D TLC NAND every day for 3 years (3000 TBW). How is that crap? Who even has such needs?

You are talking about some arbitrary "quality" - I want to be able to rewrite it a zillion times - which make no sense for 99.9% of use cases.

I'd much rather have a 4 TB drive which can be rewritten 1000 times versus a same price 256 GB one which can be rewritten 1 million times.

From the Terminator fandom wiki:

The CPU was modeled and designed primarily on computers in advanced 3-Dimensional programming packages, where simulated testing could be done in real time, or at increased rates.

The lattice of cubes in the construction of the prototype CPU suggests a "hypercube", a cube of more than three dimensions. In computer design, hypercubes are used as a physical connection scheme that minimizes the effective communication distance (and therefore the time delay) between processors, when the logical connection scheme needed by the software that will be run on those processors cannot be known in advance. This then supports the Neural Net's ability to learn, adapt, and built new logical connection schemes.

What real world outcomes might we expect from this technology?

Anyone know?

Faster chips which use less power to do the same amount of computation, same as ever.

CFETs are very much real world technology which are on the roadmaps for all leading edge fabs. They're the same as current gen FinFets and GAAFets a year or two from now in that they essentially just do the same thing as previous generations of chip tech except they do it better.

Novel cooling solutions, among others, one suspects.
Thicker phones.
Since it's still a GAA channel, are the channel lengths sthr same as the latest 3nm node?
A minor startup isn't Intel, Samsung and TSMC but www.thruchip.com did 3d stacking 10 years ago.

https://web.stanford.edu/class/ee380/Abstracts/141022-slides...

https://www.theregister.com/2014/02/21/thruchip_communicatio...

the case for inductive stacked chips is pretty compelling, if those slides are right!

I wonder if you can also couple adjacent chips that way, since 2.5D is, if anything, more important than stacking...

What does heat do in these chips? How does it not melt?
heat density is heat density. this technique isn't the same as stacking two logic dies (which would have a heat problem).

backside power is actually a pretty important power improvement - both delivery and cooling.

Interesting that when we can't make chips bigger laterally, we go vertical and stack transistors. It's like we discovered high-rise buildings all over again.
Is that going to increase the GHz as well or just the number of cores.
Doubt that. Frequency will be tied to heat dissipation. And in a 3d stack, the heat dissipation of the inner transistors is going to be very difficult
Doubt that. Frequency will be tied to heat dissipation. And in a 3d stack, the heat dissipation of the inner transistors is going to be very difficult
GHz might not increase but maybe they can do more IPC by having a wider architecture.
Any EE member here? How's photonics' computing going?
Interesting bit about Samsung’s secret sauce:

Samsung went even smaller than Intel, showing results for 48-nm and 45-nm contacted poly pitch (CPP), compared to Intel’s 60 nm, though these were for individual devices, not complete inverters. Although there was some performance degradation in the smaller of Samsung’s two prototype CFETs, it wasn’t much, and the company’s researchers believe manufacturing process optimization will take care of it. Crucial to Samsung’s success was the ability to electrically isolate the sources and drains of the stacked pFET and nFET devices. Without adequate isolation, the device, which Samsung calls a 3D stacked FET (3DSFET), will leak current. A key step to achieving that isolation was swapping an etching step involving wet chemicals with a new kind of dry etch. That led to an 80 percent boost in the yield of good devices. Like Intel, Samsung contacted the bottom of the device from beneath the silicon to save space. However, the Korean chipmaker differed from the American one by using a single nanosheet in each of the paired devices, instead of Intel’s three. According to its researchers, increasing the number of nanosheets will enhance the CFET’s performance.

> Experts estimate CFETs to roll out commercially seven to ten years from now, but there is still a lot of work before they are ready.

So the technology is still very much science fiction at this point.