Worth noting that 16V8 and 22V10 GALs are still being made too, and I’d argue that programmers for them aren’t exactly “outdated”.
Not that I have anything against this design, I’m always happy to see a new SBC, though it could be argued that it still “hides” more of the bus inside the MCU than would perhaps be ideal.
are cplds okay
you can get currently-manufactured cplds for under two bucks
https://www.digikey.com/en/products/filter/cplds-complex-pro...
and probably nobody is going to say that an lc4032ze or an atf1502 is faster than a z80 (i mean, it's literally faster, in the same way that a 74hc04 is, but you sure aren't going to emulate a z80 on it)
Especially for the Atmel 15xx parts, the software is windows-only, old and annoyingly crash-prone. The GALs are at least programmable from modern OSes with commodity programmers.
That said, the CPLDs themselves are good chips, and I don’t think especially inappropriate for a vintage project
The original owner of the item makes numerous small changes and repairs over decades which preserve and improve the functionality.
They finally sell it off to a collector who reverts all the changes, degrading the functionality in order to restore some notion of authenticity. And sometimes they go further, fixing “mistakes” made by the factory.
In this case, the functionality of a Z80 is so ridiculously outdated and obsolete that I suppose authenticity (and nostalgia) is really the only point.
I'd love to interface z80, 6502, 68k and such, without level shifting, to FPGAs supported by the open stack.
https://www.westerndesigncenter.com/wdc/documentation/w65c02...
https://www.westerndesigncenter.com/wdc/documentation/w65c81...
I also found digikey stocks some 68k variants that are 3v3. Sadly no 030 or 010 which are the ones I prefer, but 000 and the still expensive 060 :X.
a 6502 is about 1200 gates i think, which is very roughly 400 4-luts
https://github.com/emeb/ulx3s_6502 simulates a 6502 on a lattice ecp5, using yosys, nextpnr, and the well-known (apparently! i'd never heard of it) https://github.com/Arlet/verilog-6502 documented at https://web.archive.org/web/20230604005701/https://c-scape.n...
no word on how much of the fpga it uses
reproducing the undocumented instructions will be more work but still will probably fit
Because a minimal such system would be a decent starting point for designing modern peripherals (on the same FPGAs, reusing HDL) for the actual classic computers.
Doing everything inside the FPGA doesn't help in this case.