They claim that the chip has an "MMU". But unfortunately this doesn't seem to be a true RISC-V MMU (according to the Sv32 specification) integrated into the CPU core itself, but just a peripheral designed for memory mapped SPI flash and PSRAM. So as far as I understand there is no true process isolation with page faults and dynamic paging.
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That’s a shame, it’d be a cool and, afaik, unique feature for this niche.
Maybe Espressif will notice that there are no RV32 chips with MMU so far (at least to my knowledge); we only have 32 bit MCUs or then only 64 bits for the CPUs. Something like Cortex-A7 is missing.
The upcoming Baochip is an RV32 chip with an MMU, I believe.
https://www.bunniestudios.com/blog/2026/baochip-1x-a-mostly-...
Edit - Oops GeorgeHahn beat me to it
There’s one incoming, https://baochip.github.io/baochip-1x/ It would be great to see more.
Baochip looks very interesting, and I highly respect bunnie's work, but I can't realistically say Baochip is a viable option for me, an unprofessional tinkerer.
Does anyone know what CPU this uses? Is it their own first party design?
Not sure I understand your question, but the ESP32-S3[1] is the "CPU" here.
> Not sure I understand your question
I'm not sure why you are not sure - S3 was using Cadence's Xtensa 32-bit LX7 dual-core microprocessor, but the article on S31 only mentions "dual core" without too much detail.
That's the SoC. The CPU is a small part of it. For example they could be using an open source design like the CVA6, or a commercial design from someone like Andes.
Espressif has a designed-in-house RISC-V CPU, so far as I know.
ESP32-S31 (very different from the S3)
That's literally and exactly what I said.
To be fair to GP, I too was confused by your use of brackets here.
I wasn't trying to be obtuse.
Formal grammar / technical documentation style guides consistently define:
[ ... ] = optional
{ ... } = repetition
| = alternatives